Empowering Next-Gen Chip Design
Multithreaded Processing
Designed with a thread-parallel architecture that utilizes all available CPU cores to accelerate rule evaluation and geometric computation. Each rule or chip region is intelligently partitioned for optimal concurrency.
TCL Scripting Support
Complete TCL interpreter embedded for rule customization, batch scripting, flow automation, and parameter tuning. All rule decks and reports are TCL-extensible.
Extensive Documentation
Over 3000 pages of fully indexed user guides, developer references, and integration manuals—covering DRC, LVS, scripting, file formats, and debug workflows.
Application Notes
Includes a library of 50+ application notes covering real-world design problems, debugging cases, optimization tips, and best practices across technology nodes.
24x7 Support
Dedicated support engineers available globally to resolve issues with fast turnaround, including live debugging sessions, remote collaboration, and critical path triage.
GUI Debug Environment
Integrated visual interface with GDS viewer, netlist browser, and interactive rule debugger. Supports cross-probing and overlay of error markers directly on layout or schematic.
Violation Histograms
Generates statistical plots to analyze frequency, distribution, and severity of violations—helping designers identify hotspots, optimize rule coverage, and prioritize fixes.
Detailed Error Reports
Generates comprehensive and hierarchical violation reports, grouped by rule, instance, or region. Includes hyperlinks to layout and suggestions for correction.
Marker Browser
All features are backed by a marker engine that generates GDS markers and overlays to assist in pinpointing exact problem locations. Integrated into GUI for instant feedback.