Ramtera Achieves Record-Breaking 1 Trillion-Polygon DRC in 11 Hours
Ramtera Inc. proudly announces a major milestone in physical verification scalability. Its flagship product, LVR (Layout Verification Reporter), successfully completed a 1 trillion- polygon DRC (Design Rule Check) run in just 11 hours on a 128-node (1024-core) AWS cluster — setting a new benchmark for trillion-scale sign-off in the semiconductor industry.
This achievement demonstrates the scalability, speed, and practicality of distributed verification for next-generation integrated circuits. The architecture powering this breakthrough is now protected under a provisional U.S. patent filed on October 27, 2025.
Key Highlights
- Distributed execution Distributed execution with R-tree partitioning and thread-based DRC segmentation
- Near-linear performance scaling across 1024 cores
- Verified rule sets across five technology nodes (180 nm → 15 nm)
- Runtime:≈ 11 hours for a flattened layout approaching 1 trillion polygons
About LVR
LVR is Ramtera’s high-performance, multi-threaded physical verification engine supporting DRC, LVS, ERC, Density, and XOR checks. Designed for cloud and on-premise scalability, LVR enables semiconductor teams to achieve sign-off accuracy with unmatched throughput and capacity.
About Ramtera Inc.
Founded in 2024, Ramtera Inc. is a U.S.-based EDA company developing scalable verification software for advanced semiconductor designs. Ramtera’s mission is to deliver high-capacity sign-off solutions powered by multithreading and distributed cloud execution.
Ramtera’s ecosystem includes partnerships and collaborations with Broadcom (Technology Alliance Partner), Intel (Technical Alliance Associate), VMware, and European research institutes such as IHP-GmbH.
The company is also an official Partner in the Amazon Partner Network (APN), a Google Cloud Partner, and an AWS Technology Partner, enabling optimized scalability and deployment for global semiconductor workloads.
Upcoming Events
Ramtera will showcase its trillion-scale verification architecture at leading global semiconductor conferences in 2026:
- Chiplet Summit 2026 Santa Clara, CA — Booth #212 (Feb 17–19, 2026)
- Design Automation Conference (DAC), Long Beach, CA — Booth #637 (July 2026)
Visitors will experience live demonstrations of trillion-scale DRC verification and learn how LVR is redefining scalability in physical verification.
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